(a) Field of the Invention
The present invention relates to a level shifter and a display using the same. More specifically, the present invention relates to a level shifter of which power efficiency is increased and a flat panel display using the same.
(b) Description of the Related Art
FIG. 1 shows a circuit diagram for representing a conventional level shifter. The conventional level shifter includes positive-channel metal oxide semiconductor (PMOS) transistors M1A, M2A, and negative-channel metal oxide semiconductor (NMOS) transistors M3A, M4A. The transistors M1A, M2A are cross-connected. An input voltage Vin is applied to a gate of the transistor M3A. An inverted voltage Vinb of the input voltage Vin is applied to a gate of the transistor M4A.
In the conventional level shifter, a voltage level of output signal Vout is varied according to the variation in values of the input voltages Vin, Vinb applied to the gates of the transistors M3A, M4A, and therefore it has been a problem that the conventional transistor is sensitive to skew of the input voltages Vin, Vinb.
FIG. 2 shows a circuit diagram for representing another conventional level shifter. The level shifter shown in FIG. 2 is different from the level shifter shown in FIG. 1 in that a transistor M1B of the level shifter shown in FIG. 2 is diode-connected and a gate of the transistor M1B is coupled to a gate of a transistor M2B of the level shifter shown in FIG. 2.
In the level shifter shown in FIG. 2, it has been a problem that a path of a static current flow is generated from a power source LVDD to a power source VSS while an output voltage is output according to an input voltage. Accordingly, power consumption of the level shifter is problematically increased.